Optimal repeater insertion for N-tier multilevel interconnect architectures

被引：2

作者：

Venkatesan, R ^{[1
]}

Davis, JA ^{[1
]}

Bowman, KA ^{[1
]}

Meindl, JD ^{[1
]}

机构：

[1] Georgia Inst Technol, Sch Elect & Comp Engn, Atlanta, GA 30332 USA

来源：

PROCEEDINGS OF THE IEEE 2000 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE | 2000年

关键词：

D O I：

10.1109/IITC.2000.854303

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new methodology to optimally insert repeaters for n-tier multilevel interconnect architectures is demonstrated. For a 0.1 mu m ASIC macrocell case study, repeater insertion either decreases the macrocell area 4-fold (and lowers power dissipation by 50%), increases clock frequency by 22% or reduces number of metal levels by 25%.

引用

页码：132 / 134

页数：3

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