High-performance 0.1-mu m-self-aligned-gate GaAs MESFET technology

We report on 0.1-mu m gate-length self-aligned Au/WSiN-gate GaAs MESFET technology, The FET we produced using this technology has a planar structure with a selective ion-implanted channel layer and self-aligned n(+)-layers, One of the key structural parameters affecting device performance is the offset separating the gate electrode from lightly-doped source and drain n' layers, A 0.1-mu m gate length is attained by i-line photolithography using an anti-reflection top coat film and SF6 gas ECR plasma etching, We demonstrate FET uniformity in a 3-in wafer and excellent high-frequency performance, The standard deviation of the threshold voltages is 0.058 V with an average of about O V at a gate length of 0.126 mu m and the current gain cutoff frequency (f(T)) is 168 GHz at a gate length of 0.06 mu m.