Hierarchical power distribution with power tree in dozens of power domains for 90-nm low-power multi-CPU SoCs

Hierarchical power distribution with a power tree has been developed. The key features are a power-tree structure with three power-tree management rules and a distributed common power domain implementation. The hierarchical power distribution supports a fine-grained power gating with dozens of power domains, which is analogous to a fine-grained clock gating. Leakage currents of a 1000000-gate power domain were effectively reduced to 1/4000 in multi-CPU SoCs with minimal area overhead.