SOI n-MOSFET low-frequency noise measurements and modeling from room temperature up to 250 °C

被引：29

作者：

Dessard, V

Iñíguez, B

Adriaensen, S

Flandre, D

机构：

[1] Catholic Univ Louvain, Microelect Lab, B-1348 Louvain, Belgium

[2] Univ Rovira & Virgili, Dept Elect Elect & Automat Engn, Tarragona 43007, Spain

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2002年 / 49卷 / 07期

关键词：

body effects; Lorentzian; noise measurement; noise model; silicon-on-insulator (SOI) technology; thermal factors;

D O I：

10.1109/TED.2002.1013288

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper deals with SOI n-MOSFET low-frequency noise measurements, analysis, and modeling from room temperature up to 250 degreesC. We observed the occurrence of a Lorentzian-like noise component depending on bias and temperature conditions. An engineering Lorentzian model has been validated and used in order to determine the SOI floating body effect related noise, continuously from fully- to partially-depleted regimes. General considerations about low-noise high-temperature analog circuits are discussed.

引用

页码：1289 / 1295

页数：7

共 17 条

[1] Adriaensen S., 1999, HITEN 99. Third European Conference on High Temperature Electronics. (IEEE Cat. No.99EX372), P79, DOI 10.1109/HITEN.1999.827467
[2] FACCIO F, 1997, THESIS INPG FRANCE
[3] FANG ZH, 1986, IEEE T ELECTRON DEV, V33, P516, DOI 10.1109/T-ED.1986.22521
[4] Modelling and application of fully depleted SOI MOSFETs for low voltage, low power analogue CMOS circuits
Flandre, D
Ferreira, LF
Jespers, PGA
Colinge, JP
[J]. SOLID-STATE ELECTRONICS, 1996, 39 (04) : 455 - 460
[5] Fully-depleted SOICMOS technology for low-voltage low-power mixed digital/analog/microwave circuits
Flandre, D
Colinge, JP
Chen, J
De Ceuster, D
Eggermont, JP
Ferreira, L
Gentinne, B
Jespers, PGA
Viviani, A
Gillon, R
Raskin, JP
Vander Vorst, A
Vanhoenacker-Janvier, D
Silveira, F
[J]. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 1999, 21 (03) : 213 - 228
[6] SILICON-ON-INSULATOR TECHNOLOGY FOR HIGH-TEMPERATURE METAL-OXIDE-SEMICONDUCTOR DEVICES AND CIRCUITS
FLANDRE, D
[J]. MATERIALS SCIENCE AND ENGINEERING B-SOLID STATE MATERIALS FOR ADVANCED TECHNOLOGY, 1995, 29 (1-3): : 7 - 12
[7] GRAY PR, 1999, ANAL DESIGN ANALOG I
[8] A 1/F NOISE TECHNIQUE TO EXTRACT THE OXIDE TRAP DENSITY NEAR THE CONDUCTION-BAND EDGE OF SILICON
JAYARAMAN, R
SODINI, CG
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1989, 36 (09) : 1773 - 1782
[9] Lee T.H., 1998, DESIGN CMOS RADIO FR
[10] Research of high-temperature instability processes in buried dielectric of full depleted SOI MOSFET's
Nazarov, AN
Colinge, JP
Barchuk, IP
[J]. MICROELECTRONIC ENGINEERING, 1997, 36 (1-4) : 363 - 366

← 1 2 →