Complementary ferroelectric-capacitor logic for low-power logic-in-memory VLSI

被引:47
作者
Kimura, H [1 ]
Hanyu, T
Kameyama, M
Fujimori, Y
Nakamura, T
Takasu, H
机构
[1] Tohoku Univ, Grad Sch Informat Sci, Sendai, Miyagi 9808577, Japan
[2] Tohoku Univ, Res Inst Elect Commun, Sendai, Miyagi 9808577, Japan
[3] Rohm Co Ltd, Semicond Res Dev Headquarters, Kyoto 6158585, Japan
关键词
content-addressable memory (CAM); dynamic logic; ferroelectric capacitor; nonvolatile storage; pass-transistor logic; pseudo non-destructive read operation;
D O I
10.1109/JSSC.2004.827802
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A novel nonvolatile logic style, called complementary ferroelectric-capacitor (CFC) logic, is proposed for low-power logic-in-memory VLSI, in which storage elements are distributed over the logic-circuit plane. Standby currents in distributed storage elements can be cut off by using ferroelectric-based nonvolatile storage elements, and the standby power dissipation can be greatly reduced. Since the nonvolatile storage and the switching functions are merged into ferroelectric capacitors by the capacitive coupling effect, reduction of active device counts can be achieved. The use of complementary stored data in coupled ferroelectric capacitors makes it possible to perform a switching operation with small degradation of the nonvolatile charge at a low supply voltage. The restore operation can be performed by only applying the small bias across the ferroelectric capacitor, which reduces the dynamic power dissipation. Applying the proposed circuitry in a fully parallel 32-bit content-addressable memory results in about 2/3 dynamic power reduction and 1/7700 static power reduction with chip size of 113, compared to a CMOS implementation using 0.6-mum ferroelectric/CMOS.
引用
收藏
页码:919 / 926
页数:8
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