Observation of current staircase due to large quantum level spacing in a silicon single-electron transistor with low parasitic series resistance

被引：22

作者：

Saitoh, M

Hiramoto, T

机构：

[1] Univ Tokyo, Inst Ind Sci, Meguro Ku, Tokyo 1538505, Japan

[2] Univ Tokyo, VLSI Design & Educ Ctr, Tokyo 1538505, Japan

来源：

JOURNAL OF APPLIED PHYSICS | 2002年 / 91卷 / 10期

关键词：

D O I：

10.1063/1.1471928

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

We have fabricated a silicon point-contact channel single-electron transistor (SET) with an ultrasmall dot. By narrowing only the point-contact region and suppressing the parasitic series resistance, a peak conductance as large as 8.8 muS and single-electron addition energy as large as 128 meV are simultaneously obtained. A current staircase due to the large quantum level spacing is clearly observed at low temperatures. From numerical calculations, it is found that the staircase feature due to discrete quantum levels stands out even at room temperature in future silicon SETs with an ultrasmall dot. (C) 2002 American Institute of Physics.

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页码：6725 / 6728

页数：4

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