Circuit-Level Impact of a-Si:H Thin-Film-Transistor Degradation Effects

被引：37

作者：

Allee, David R. ^{[1
]}

Clark, Lawrence T. ^{[1
]}

Vogt, Bryan D. ^{[1
]}

Shringarpure, Rahul ^{[1
]}

Venugopal, Sameer M. ^{[1
]}

Uppili, Shrinivas Gopalan ^{[1
]}

Kaftanoglu, Korhan ^{[1
]}

Shivalingaiah, Hemanth ^{[1
]}

Li, Zi P. ^{[1
]}

Fernando, J. J. Ravindra ^{[1
]}

Bawolek, Edward J. ^{[1
]}

O'Rourke, Shawn M. ^{[1
]}

机构：

[1] Arizona State Univ, Flexible Display Ctr, Tempe, AZ 85284 USA

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2009年 / 56卷 / 06期

关键词：

Amorphous silicon; flexible electronics; thin-film transistors (TFTs); threshold-voltage shift; THRESHOLD-VOLTAGE DEGRADATION; H TFTS; BIAS-STRESS; DEFECT POOL; INSTABILITY; INTEGRATION; DEPENDENCE; DISPLAYS;

D O I：

10.1109/TED.2009.2019387

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper reviews amorphous silicon thin-film-transistor (TFT) degradation with electrical stress, examining the implications for various types of circuitry. Experimental measurements on active-matrix backplanes, integrated a-Si:H column drivers, and a-Si:H digital circuitry are performed. Circuit modeling that enables the prediction of complex-circuit degradation is described. The similarity of degradation in amorphous silicon to negative bias temperature instability in crystalline PMOS FETs is discussed as well as approaches in reducing the TFT degradation effects. Experimental electrical-stress-induced degradation results in controlled humidity environments are also presented.

引用

页码：1166 / 1176

页数：11

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