Ensemble Monte Carlo study of interface-state generation in low-voltage scaled silicon MOS devices

An ensemble Monte Carlo (MC) model coupled with an interface-state generation model was employed to predict the quantity and lateral distribution of hot-electron-induced interface states in scaled silicon MOSFET's. Constant field and more generalized scaling methods were used as the basis to simulate devices with 0.33-, 0.20-, and 0.12-mu m channel lengths. The dependencies of interface-state generation on applied bias and electric field profiles were investigated. Hot-electron injection and interface-state density profiles were simulated at biases as low as 1.34 V (i.e., lower than the 3.1 V potential barrier at the Si/SiO2 interface). These simulations demonstrate that ''lucky electron'' and/or electron temperature models are no longer accurate for predicting hot-electron effects in such regimes. Electron-electron scattering is shown to be a critical consideration for simulation of hot-electron injection at low drain to source bias voltages, where local interfacial barrier heights are greater than the energy gained by an electron from the applied electric field. Simulations indicate that a scaled decrease in the channel length of a device may be accompanied by an increase in the lateral electric field without incurring a penalty for higher hot-electron degradation. It is also shown that conventional hot-electron stressing using accelerated stress bias conditions may continue to be valuable for predicting the reliability of device designs scaled to 0.1-mu m channel lengths.