Transient analysis of CML inverter using Monte Carlo simulations

Monte Carlo simulation of a complete CML gate composed of two submicron bipolar transistors has been performed. The gate delay time tau(D) is usually calculated, according to a widely-used formula, as a weighted sum of time constants deduced from the transistor small-signal parameters. In this paper we analyse the validity of this approach. The weighting factor values, used in the tau(D) expression are determined from this expression and transient Monte Carlo simulation results. Comparison between these results and those given in the literature shows that the best agreement is obtained if two conditions are fulfilled: the transit time used in the tau(D) expression is reduced to the intrinsic base transit time, and the access base resistance is limited to the extrinsic one. However, even in this case, the weighting factors associated with depletion capacitances are called into question by the Monte Carlo analysis. A set of weighting factor values is proposed, which leads to a discrepancy between the simulated and calculated tau(D) within 10%.