MAXIMUM OPERATING FREQUENCY IN SI BIPOLAR MASTER-SLAVE TOGGLE FLIP-FLOP CIRCUIT

被引:9
作者
ISHII, K
ICHINO, H
YAMAGUCHI, C
机构
[1] NTT LSI Laboratories, Atsugi-shi, Kanagawa 243-01, 3-1, Morinosato Wakamiya
关键词
D O I
10.1109/4.303712
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a propagation-delay equation which is expressed as the influence of the individual device and circuit parameters on the maximum operating frequency of Si bipolar master-slave toggle flip-flop (MS-TFF) circuit with double feedback emitter followers. This equation shows that optimizing the size of individual transistors can enhance the operating speed. Test results show a 10% increase in operating frequency by adopting this design technique. It is also shown that the time constants R(B)C(jC), R(B)C(D), tau(F), R(L)C(jC), and R(C)C(jC) of the upper-level current switch and tau(F) of the second feedback emitter follower greatly affect the operating speed of circuits using recently developed Si bipolar transistors. The results predicted by the equation are in good agreement with both the experimental ones and SPICE simulations.
引用
收藏
页码:754 / 760
页数:7
相关论文
共 16 条
[1]   A PROPAGATION-DELAY EXPRESSION AND ITS APPLICATION TO THE OPTIMIZATION OF POLYSILICON EMITTER ECL PROCESSES [J].
CHOR, EF ;
BRUNNSCHWEILER, A ;
ASHBURN, P .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1988, 23 (01) :251-259
[2]   5-GBIT/S SI INTEGRATED REGENERATIVE DEMULTIPLEXER AND DECISION CIRCUIT [J].
CLAWIN, D ;
LANGMANN, U ;
SCHREIBER, HU .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1987, 22 (03) :385-389
[3]   AN ANALYTICAL MAXIMUM TOGGLE FREQUENCY EXPRESSION AND ITS APPLICATION TO OPTIMIZING HIGH-SPEED ECL FREQUENCY-DIVIDERS [J].
FANG, W ;
BRUNNSCHWEILER, A ;
ASHBURN, P .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1990, 25 (04) :920-931
[4]   ACCURATE ANALYTICAL DELAY EXPRESSIONS FOR ECL AND CML CIRCUITS AND THEIR APPLICATIONS TO OPTIMIZING HIGH-SPEED BIPOLAR CIRCUITS [J].
FANG, W .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1990, 25 (02) :572-583
[5]  
FELDER A, 1993, ISSCC 93, P156
[6]  
ISHII K, 1992, PROCEEDINGS OF THE 1992 BIPOLAR / BICMOS CIRCUITS AND TECHNOLOGY MEETING, P147, DOI 10.1109/BIPOL.1992.274063
[7]  
KIRK CT, 1962, IRE T ELECTRON DEV, V9, P164
[8]  
KOBAYASHI Y, 1992, 1992 P IEICE FAL C, P5
[9]   A 20-PS SI BIPOLAR IC USING ADVANCED SUPER SELF-ALIGNED PROCESS TECHNOLOGY WITH COLLECTOR ION-IMPLANTATION [J].
KONAKA, S ;
YAMAMOTO, E ;
SAKUMA, K ;
AMEMIYA, Y ;
SAKAI, T .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1989, 36 (07) :1370-1375
[10]  
MEYER CS, 1968, ANAL DESIGN INTEGRAT