Line edge roughness impact on critical dimension variation

Critical Dimension (CD) uniformity control across wafer becomes more and more statistically limited with the continuous aggressive scaling of transistor gate. In the limit due to line edges are self-affine, correlation length and fractal dimension are two parameters that affect the roughness contribution to a given spatial frequency in addition to the standard deviation value which is usually called line edge roughness (LER). In this paper, we will focus on the random contributions instead of systematic ones, particularly from the perspective of LER. The following issues are addressed: How these individual factors affect the CD uniformity from the statistical perspective; How to translate these factors into the processing terms; and finally how to balance these factors to achieve the ultimate CD control goal. Our study is based on both simulation and experimental approach. On the simulation side, the line edges are generated with power spectral density (PSD) which is a function of standard deviation, correlation length and fractal dimension. The dependence of CD uniformity on these factors can be extracted from tens of thousands of simulated edges. We found out that the relationship between the CD variation and the correlation length becomes logarithmic when the gate width is scaled to a degree comparable to the correlation length. On the experimental side, by analyzing the Scanning Electron Microscopy (SEM) images from pre- and post-etching patterns, the process-related implications of these factors on the CD uniformity can be derived. Finally by combining the modeling and experimental data, we will discuss how to trade off these parameters to control the CD variations.