Modeling of large-grain polysilicon formation under retardation effect of SPC

被引：9

作者：

Cheng, CF ^{[1
]}

Leung, TC ^{[1
]}

Poon, MC ^{[1
]}

Kok, CW ^{[1
]}

Chan, MS ^{[1
]}

机构：

[1] Hong Kong Univ Sci & Technol, Dept Elect & Elect Engn, Kowloon, Hong Kong, Peoples R China

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2004年 / 51卷 / 12期

关键词：

crystallization; large-grain; polysilicon; thermal annealing; thin-film transistor (TFT);

D O I：

10.1109/TED.2004.838323

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper details the study of the mechanism of large-grain polysilicon layer formations using metal-induced lateral crystallization (MILC). A model is proposed to predict the growth rate of MILC under the retardation effect of solid-phase crystallization (SPC) at different annealing conditions. The model has been extensively validated by experimental data. This paper will show that the SPC exists as a counter-effect to retard the MILC and degrade the superiority of the polysilicon layer. The model has been used to predict the MILC rate of large-grain polysilicon grown by a pulsed-annealing technique that suppresses the undesirable SPC effect. The model prediction agrees well with the experimental results.

引用

页码：2205 / 2210

页数：6

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