Self-aligned, vertical-channel, polymer field-effect transistors

被引:475
作者
Stutzmann, N [1 ]
Friend, RH [1 ]
Sirringhaus, H [1 ]
机构
[1] Univ Cambridge, Cavendish Lab, Cambridge CB3 0HE, England
关键词
D O I
10.1126/science.1081279
中图分类号
O [数理科学和化学]; P [天文学、地球科学]; Q [生物科学]; N [自然科学总论];
学科分类号
07 ; 0710 ; 09 ;
摘要
The manufacture of high-performance, conjugated polymer transistor circuits on flexible plastic substrates requires patterning techniques that are capable of defining critical features with submicrometer resolution. We used solid-state embossing to produce polymer field-effect transistors with submicrometer critical features in planar and vertical configurations. Embossing is used for the controlled microcutting of vertical sidewalls into polymer multilayer structures without smearing. Vertical-channel polymer field-effect transistors on flexible poly(ethylene terephthatate) substrates were fabricated, in which the critical channel length of 0.7 to 0.9 micrometers was defined by the thickness of a spin-coated insulator layer. Gate electrodes were self-aligned to minimize overlap capacitance by inkjet printing that used the embossed grooves to define a surface-energy pattern.
引用
收藏
页码:1881 / 1884
页数:4
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