Characterization and reliability of dual high-k gate dielectric stack (poly-Si-HfO2-SiO2) prepared by in situ RTCVD process for system-on-chip applications

We investigate for the first time the possibility of integrating chemical vapor deposition (CVD) HfO2 into the multiple gate dielectric system-on-a-chip (SoC) process in the range of 6-7 mn, which supports higher voltage (2.5-5-V operation/tolerance). Results show that CVD HfO2-SiO2 stacked gate dielectric (EOT = 6.2 nm) exhibits lower leakage current than that of SiO2 (EOT = 5.7 nm) by a factor of similar to10(2), with comparable interface quality (D-it similar to 1 X 10(10) cm(-2)eV(-1)). The presence of negative fixed charge is observed in HfO2-SiO2 gate stack. In addition, the addition of HfO2 on SiO2 does not alter the dominant conduction mechanism of Fowler-Nordheim tunneling in HfO2-SiO2 gate stack. Furthermore, the HfO2-SiO2 gate stack shows longer time to breakdown TB D than SiO2 under constant voltage stress. These results suggest that it may be feasible to use such a gate stack for higher voltage operation in SoC, provided other key requirements such as V-t stability (charge trapping under stress) can be met and the negative fixed charge eliminated.