A high performance 100 nm generation SOC technology [CMOS IV] for high density embedded memory and mixed signal LSIs

被引：18

作者：

Miyashita, K ^{[1
]}

Nakayama, T ^{[1
]}

Oishi, A ^{[1
]}

Hasumi, R ^{[1
]}

Owada, M ^{[1
]}

Aota, S ^{[1
]}

Okayama, Y ^{[1
]}

Matsumoto, M ^{[1
]}

Igarashi, H ^{[1
]}

Yoshida, T ^{[1
]}

Kasai, K ^{[1
]}

Yoshitomi, T ^{[1
]}

Fukaura, Y ^{[1
]}

Kawasaki, H ^{[1
]}

Ishimaru, K ^{[1
]}

Adachi, K ^{[1
]}

Fujiwara, M ^{[1
]}

Ohuchi, K ^{[1
]}

Takayanagi, M ^{[1
]}

Oyamatsu, H ^{[1
]}

Matsuoka, F ^{[1
]}

Noguchi, T ^{[1
]}

Kakumu, M ^{[1
]}

机构：

[1] Toshiba Co Ltd, Syst LSI Div, Isogo Ku, Yokohama, Kanagawa 2358522, Japan

来源：

2001 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2001年

关键词：

D O I：

10.1109/VLSIT.2001.934922

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

This paper demonstrates a 100 nm generation SOC technology [CMOS IV] for the first time. Three types of core devices are presented with optimized gate oxynitrides for their stand-by power conditions. This advanced LOGIC process is compatible with 0.18 mum(2) trench capacitor DRAM and 1.25 mum(2) 6 Tr. SRAM. Two kinds of high V-dd devices can be prepared by triple gate oxide process. Moreover, for mixed signal applications, Ta2O5 MIM capacitors are introduced into Cu and low-k interconnects.

引用

页码：11 / 12

页数：2

共 10 条

[1] Extending gate dielectric scaling limit by NO oxynitride: Design and process issues for sub-100 nm technology [J].

Fujiwara, M ;

Takayanagi, M ;

Shimizu, T ;

Toyoshima, Y .

INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, :227-230

[2] A modular 0.13 μm bulk CMOS technology for high performance and low power applications [J].

Han, LK ;

Biesemans, S ;

Heidenreich, J ;

Houlihan, K ;

Lin, C ;

McGahay, V ;

Schiml, T ;

Schmidt, A ;

Schroeder, UP ;

Stetter, M ;

Wann, C ;

Warner, D ;

Mahnkopf, R ;

Chen, B .

2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2000, :12-13

[3]

HU JC, 2000, S VLSI TECH, P188

[4] CMOS device optimization for system-on-a-chip applications [J].

Imai, K ;

Yamaguchi, K ;

Kudo, T ;

Kimizuka, N ;

Onishi, H ;

Ono, A ;

Nakahara, Y ;

Goto, Y ;

Noda, K ;

Masuoka, S ;

Ito, S ;

Matsui, K ;

Ando, K ;

Ohashi, EHT ;

Oda, N ;

Yokoyama, K ;

Takewaki, T ;

Sone, S ;

Horiuchi, T .

INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, :455-458

[5]

KOKUBUN K, 1999, S VLSI TECH, P155

[6]

Miyashita K., 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), P645, DOI 10.1109/IEDM.1999.824235

[7] A versatile 0.13 μm CMOS Platform Technology supporting High Performance and Low Power Applications [J].

Perera, AH ;

Smith, B ;

Cave, N ;

Sureddin, M ;

Chheda, S ;

Singh, R ;

Islam, R ;

Chang, J ;

Song, SC ;

Sultan, A ;

Crown, S ;

Kolagunta, V ;

Shah, S ;

Celik, M ;

Wu, D ;

Yu, KC ;

Fox, R ;

Park, S ;

Simpson, C ;

Eades, D ;

Gonzales, S ;

Thomas, C ;

Sturtevant, J ;

Bonser, D ;

Benavides, N ;

Thompson, M ;

Sheth, V ;

Fretwell, J ;

Kim, S ;

Ramani, N ;

Green, K ;

Moosa, M ;

Besser, P ;

Solomentsev, Y ;

Denning, D ;

Friedemann, M ;

Baker, B ;

Chowdhury, R ;

Ufmani, S ;

Strozewski, K ;

Carter, R ;

Reiss, J ;

Olivares, M ;

Ho, B ;

Lii, T ;

Sparks, T ;

Stephens, T ;

Schaller, M ;

Goldberg, C ;

Junker, K .

INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, :571-574

[8] A 130 nm generation logic technology featuring 70nm transistors, dual Vt transistors and 6 layers of Cu interconnects [J].

Tyagi, S ;

Alavi, M ;

Bigwood, R ;

Bramblett, T ;

Brandenburg, J ;

Chen, W ;

Crew, B ;

Hussein, M ;

Jacob, P ;

Kenyon, C ;

Lo, C ;

Mcintyre, B ;

Ma, Z ;

Moon, P ;

Nguyen, P ;

Rumaner, L ;

Schweinfurth, R ;

Sivakumar, S ;

Stettler, M ;

Thompson, S ;

Tufts, B ;

Xu, J ;

Yang, S ;

Bohr, M .

INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, :567-570

[9] A CMOS technology platform for 0.13μm generation SOC(system on a chip) [J].

Yoshimura, H ;

Nakayama, T ;

Nishigohri, M ;

Inohara, M ;

Miyashita, K ;

Morifuji, E ;

Oishi, A ;

Kawashima, H ;

Habu, M ;

Koike, H ;

Takato, H ;

Toyoshima, Y ;

Ishiuchi, H .

2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2000, :144-145

[10] A 0.13 μm CMOS technology with 193 nm lithography and Cu/low-k for high performance applications [J].

Young, KK ;

Wu, SY ;

Wu, CC ;

Wang, CH ;

Lin, CT ;

Cheng, JY ;

Chiang, M ;

Chen, SH ;

Lo, TC ;

Chen, YS ;

Chen, JH ;

Chen, LJ ;

Hou, SY ;

Liaw, JJ ;

Chang, TE ;

Hou, CS ;

Shih, J ;

Jeng, SM ;

Hsieh, HC ;

Ku, Y ;

Yen, T ;

Tao, H ;

Chao, LC ;

Shue, S ;

Jang, SM ;

Ong, TC ;

Yu, CH ;

Liang, MS ;

Diaz, CH ;

Sun, JYC .

INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, :563-566

← 1 →