A four-level storage 4-Gb DRAM

被引:38
作者
Okuda, T
Murotani, T
机构
[1] ULSI Device Development Laboratories, NEC Corporation, Sagamihara
[2] Keio University, Kanagawa
[3] NEC Corporation, Kawasaki
[4] ULSI Device Development Laboratories, Sagamihara
[5] Yokohama National University, Yokohama
[6] Tokyo Institute of Technology, Tokyo
关键词
BST; DRAM; hierarchical bit-line architecture; multilevel; time-shared sensing scheme;
D O I
10.1109/4.641695
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A 4-Gb DRAM with multilevel-storage memory cells has been developed, This large memory capacity is achieved by storing data at four levels, each corresponding to two-bit-data storage in a single memory cell, The four-level storage reduces the effective cell size by 50%, A sense amplifier using charge coupling and charge sharing was developed for the four-level sensing and restoring, The sense amplifier uses a hierarchical bit-line scheme and operates in a time-sharing mode, thus reducing the sense amplifier area, A 4-Gb DRAM fabricated using 0.15-mu m CMOS technology measures 986 mm(2). The memory cell is 0.23 mu m(2). Its capacitance of 60 fF is achieved by using a high-dielectric-constant material BST.
引用
收藏
页码:1743 / 1747
页数:5
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