Loading effects in deep silicon etching

Feature scale pattern dependencies (microloading and aspect ratio dependent etching) and chip and wafer level loading effects complicate the use of deep silicon etching in MEMS applications. They have major effect on uniformity and etch rate on the wafer scale and on a feature scale. The aim of this study was to find the limitations that these phenomenon set on deep silicon etching. Wafer scale (100 mm or 150 mm), chip scale (1-10 mm) and feature scale (1-1000 mum) structures were etched in pulsed ICP (Bosch process, SF6/C4F8). Etched depths were 10-500 mum, and aspect ratios up to 20:1. Strong dependence of etch rate on loading was observed. On the wafer scale average etch rate was greatly reduced, from 5.4 mum/min (8% load, 2 mm feature size) to 1.7 mum/min (100% load). At same time uniformity deteriorated from excellent 2% to 35% which is too high value for practical applications. Chip pattern density did not affect etch rate on an isolated small chips (2.5 x 2.5 mm(2)) but for 10 x 10 mm(2) chip 10% etch rate reduction was seen at high chip scale load. In this case wafer scale etchable area was 6%. We show that feature scale and wafer scale pattern dependies in ICP etching are strongly coupled.