Modeling of tunneling currents through HfO2 and (HfO2)x (Al2O3)1-x gate stacks

被引：52

作者：

Hou, YT ^{[1
]}

Li, MF

Yu, HY

Kwong, DL

机构：

[1] Natl Univ Singapore, Dept Elect & Comp Engn, Silicon Nano Device Lab, Singapore 119260, Singapore

[2] Univ Texas, Dept Elect & Comp Engn, Austin, TX 78752 USA

来源：

IEEE ELECTRON DEVICE LETTERS | 2003年 / 24卷 / 02期

关键词：

CMOS scaling; HfO2; (HfO2)(x) (Al2O3)(1-x); high-kappa gate dielectric stacks; tunneling current;

D O I：

10.1109/LED.2002.807708

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We present a physical modeling of tunnelling currents through ultrathin high-kappa gate stacks which includes an ultrathin interface layer, both electron and hole quantization in the substrate and gate electrode, and energy band offsets between high-kappa. dielectrics and Si determined from high-resolution XPS. Excellent agreements between simulated and experimentally measured tunneling currents have been obtained for chemical vapor deposited and physical vapor deposited HfO2 with and without NH3-based interface layers, and ALD Al2O3 gate stacks with different EOT and bias polarities. This model is applied to more thermally stable (HfO2)(x)(Al2O3)(1-x). gate stacks in order to project their scalability for future CMOS applications.

引用

页码：96 / 98

页数：3

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