THE DESIGN AND OPTIMIZATION OF HIGH-PERFORMANCE, DOUBLE-POLY SELF-ALIGNED P-N-P TECHNOLOGY

This paper describes the device design and performance of a double-poly self-aligned p-n-p technology, featuring a low-resistivity p+ subcollector, thin p-epi, and boron-doped poly-emitter. Device isolation was provided by deep and shallow trenches which reduce the collector-to-substrate capacitance while maintaining a high breakdown voltage (greater-than-or-equal-to 40 V). By utilizing a shallow emitter process in conjunction with an optimized arsenic-base implant, devices with emitter-base junction depths as shallow as 20 nm, and base widths less than 100 nm were obtained. Cut-off frequencies up to 27 GHz were obtained, and the ac performance was demonstrated by an NTL-gate delay of 36 pS, and an active-pull-down (APD) ECL-gate delay of 20 pS. This high-performance p-n-p technology was developed to be compatible with existing double-poly n-p-n technologies. Thus the matching speed of p-n-p devices opens up new opportunities for high-performance complementary bipolar circuits.