A 17-NS 4-MB CMOS DRAM

被引：6

作者：

NAGAI, T

NUMATA, K

OGIHARA, M

SHIMIZU, M

IMAI, K

HARA, T

YOSHIDA, M

SAITO, Y

ASAO, Y

SAWADA, S

FUJII, S

机构：

[1] TOSHIBA CO LTD,ULSI RES CTR,KAWASAKI 210,JAPAN

[2] TOSHIBA CO LTD,DEPT MEMORY IC ENGN,KAWASAKI 210,JAPAN

[3] TOSHIBA CO LTD,TOSHIBA RES & DEV CTR,KAWASAKI 210,JAPAN

[4] TOSHIBA MICROELECTRON CORP,SAIWAI KU,KAWASAKI 210,JAPAN

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1991年 / 26卷 / 11期

关键词：

D O I：

10.1109/4.98969

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 17-ns nonaddress-multiplexed 4-Mb DRAM fabricated with a pure CMOS process is presented. The RAM incorporates a direct bit-line sensing technique with a two-stage current-mirror readout amplifier. The high sensitivity of a current-mirror amplifier enables a small bit-line signal to be amplified without waiting for the start of the bit-line latch action. The chip measures 4.76 x 11.06 mm2 with x 1/x 4 organization.

引用

页码：1538 / 1543

页数：6

共 11 条

[1] A 45-NS 16-MBIT DRAM WITH TRIPLE-WELL STRUCTURE [J].

FUJII, S ;

OGIHARA, M ;

SHIMIZU, M ;

YOSHIDA, M ;

NUMATA, K ;

HARA, T ;

WATANABE, S ;

SAWADA, S ;

MIZUNO, T ;

KUMAGAI, J ;

YOSHIKAWA, S ;

KAKI, S ;

SAITO, Y ;

AOCHI, H ;

HAMAMOTO, T ;

TOITA, K .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1989, 24 (05) :1170-1175

[2]

FURUYAMA J, 1990, INT J HIGH SPEED ELE, V1, P183

[3] TRENDS IN MEGABIT DRAM CIRCUIT-DESIGN [J].

ITOH, K .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1990, 25 (03) :778-789

[4] AN EXPERIMENTAL 1-MBIT BICMOS DRAM [J].

KITSUKAWA, G ;

HORI, R ;

KAWAJIRI, Y ;

WATANABE, T ;

KAWAHARA, T ;

ITOH, K ;

KOBAYASHI, Y ;

OOHAYASHI, M ;

ASAYAMA, K ;

IKEDA, T ;

KAWAMOTO, H .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1987, 22 (05) :657-662

[5] A 23-NS 1-MB BICMOS DRAM [J].

KITSUKAWA, G ;

YANAGISAWA, K ;

KOBAYASHI, Y ;

KINOSHITA, Y ;

OHTA, T ;

UDAGAWA, T ;

MIWA, H ;

MIYAZAWA, H ;

KAWAJIRI, Y ;

OUCHI, Y ;

TSUKADA, H ;

MATSUMOTO, T ;

ITOH, K .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1990, 25 (05) :1102-1111

[6] A 22-NS 1-MBIT CMOS HIGH-SPEED DRAM WITH ADDRESS MULTIPLEXING [J].

LU, NCC ;

BRONNER, GB ;

KITAMURA, K ;

SCHEUERLEIN, RE ;

HENKELS, WH ;

DHONG, SH ;

KATAYAMA, Y ;

KIRIHATA, T ;

NIIJIMA, H ;

FRANCH, RL ;

HWANG, W ;

NISHIWAKI, M ;

PESAVENTO, FL ;

RAJEEVAKUMAR, TV ;

SAKAUE, Y ;

SUZUKI, Y ;

IGUCHI, Y ;

YANO, E .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1989, 24 (05) :1198-1205

[7] A 20-NS 128-KBIT X 4 HIGH-SPEED DRAM WITH 330-MBIT/S DATA RATE [J].

LU, NCC ;

CHAO, HH ;

HWANG, W ;

HENKELS, WH ;

RAJEEVAKUMAR, TV ;

HANAFI, HI ;

TERMAN, LM ;

FRANCH, RL .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1988, 23 (05) :1140-1149

[8]

LU NCC, 1988, ISSCC, P240

[9]

WATANABE S, 1987 S VLSI CIRC DIG, P79

[10]

Yanagisawa Kazumasa, 1989, ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference, P184

← 1 2 →