A 3.3-V 12-NS 16-MB CMOS SRAM

被引：12

作者：

GOTO, H ^{[1
]}

OHKUBO, H ^{[1
]}

KONDOU, K ^{[1
]}

OHKAWA, M ^{[1
]}

MITANI, H ^{[1
]}

HORIBA, S ^{[1
]}

SOEDA, M ^{[1
]}

HAYASHI, F ^{[1
]}

HACHIYA, Y ^{[1
]}

SHIMIZU, T ^{[1
]}

ANDO, M ^{[1
]}

MATSUDA, Z ^{[1
]}

机构：

[1] NEC CORP LTD,ULSI DEVICE DEV LABS,SAGAMIHARA,KANAGAWA 229,JAPAN

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1992年 / 27卷 / 11期

关键词：

D O I：

10.1109/4.165327

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 16-Mb CMOS SRAM having an access time of 12 ns under a 3.3-V supply has been developed with 0.4-mum process technology. An address access time of 12 ns has been achieved by an optimized architecture, the use of an automated transistor size optimizer, and a read-bus midlevel preset scheme (RBMIPS). For better yield and efficient testing, an on-chip test circuit with three test modes has been implemented.

引用

页码：1490 / 1496

页数：7

共 10 条

[1] A 15-NS 4-MB CMOS SRAM [J].

AIZAKI, S ;

SHIMIZU, T ;

OHKAWA, M ;

ABE, K ;

AIZAKI, A ;

ANDO, M ;

KUDOH, O ;

SASAKI, I .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1990, 25 (05) :1063-1067

[2] A 20-NS 4-MB CMOS SRAM WITH HIERARCHICAL WORD DECODING ARCHITECTURE [J].

HIROSE, T ;

KURIYAMA, H ;

MURAKAMI, S ;

YUZURIHA, K ;

MUKAI, T ;

TSUTSUMI, K ;

NISHIMURA, Y ;

KOHNO, Y ;

ANAMI, K .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1990, 25 (05) :1068-1074

[3]

KATO H, 1992, FEB ISSCC DIG TECH P, P210

[4] A 25-NS 4-MBIT CMOS SRAM WITH DYNAMIC BIT-LINE LOADS [J].

MIYAJI, F ;

MATSUYAMA, Y ;

KANAISHI, Y ;

SENOH, K ;

EMORI, T ;

HAGIWARA, Y .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1989, 24 (05) :1213-1218

[5] A 21-MW 4-MB CMOS SRAM FOR BATTERY OPERATION [J].

MURAKAMI, S ;

FUJITA, K ;

UKITA, M ;

TSUTSUMI, K ;

INOUE, Y ;

SAKAMOTO, O ;

ASHIDA, M ;

NISHIMURA, Y ;

KOHNO, Y ;

NISHIMURA, T ;

ANAMI, K .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1991, 26 (11) :1563-1570

[6]

NAKAMURA K, 1992, FEB ISSCC DIG TECH P, P212

[7]

Ohkubo H., 1991, International Electron Devices Meeting 1991. Technical Digest (Cat. No.91CH3075-9), P481, DOI 10.1109/IEDM.1991.235351

[8] A 4-MB CMOS SRAM WITH A PMOS THIN-FILM-TRANSISTOR LOAD CELL [J].

OOTANI, T ;

HAYAKAWA, S ;

KAKUMU, M ;

AONO, A ;

KINUGAWA, M ;

TAKEUCHI, H ;

NOGUCHI, K ;

YABE, T ;

SATO, K ;

MAEGUCHI, K ;

OCHII, K .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1990, 25 (05) :1082-1092

[9] A 23-NS 4-MB CMOS SRAM WITH 0.2-MU A STANDBY CURRENT [J].

SASAKI, K ;

ISHIBASHI, K ;

SHIMOHIGASHI, K ;

YAMANAKA, T ;

MORIWAKI, N ;

HONJO, S ;

IKEDA, S ;

KOIKE, A ;

MEGURO, S ;

MINATO, O .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1990, 25 (05) :1075-1081

[10]

SINOHARA H, 1985, FEB ISSCC DIG TECH P, P62

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