EFFECTS OF LATTICE MISMATCH AND THERMAL ANNEALING ON DEEP TRAPS AND INTERFACE STATES IN GA0.92IN0.08AS(N+)/GAAS(P) HETEROJUNCTIONS

The effects of the lattice-mismatch-induced defects on deep level traps in Ga0.92In0.08As(n+)/GaAs(p) heterojunction diodes have been studied by means of various deep level transient spectroscopy techniques and the frequency-dependent capacitance-voltage (C-V-f) characteristics. Three hole traps at 0.58, 0.42, and 0.27 eV were observed. We attribute the 0.42 eV trap to Cu impurity, the 0.58 eV trap to V(Ga) or Fe, and the 0.27 eV trap to a complex associated with the 0.42 and 0.58 eV traps. Depth profiles of these hole traps in the GaAs side were measured in different lattice-mismatched samples. The depth profile data near the interface and from deep inside the bulk show evidence of impurity gettering by the mismatched interface. We also found that the concentrations of these traps were reduced by rapid thermal annealing. A U-shaped energy distribution of the interface states was obtained from the C-V-f measurements. For an in-plane mismatch greater than 0.25%, the interface state density shows no obvious dependence on the in-plane lattice mismatch, while at smaller mismatch the interface state density increases with increasing mismatch. The interface state density was on the order of 10(11) cm-2.