MODELING HOT-CARRIER EFFECTS IN POLYSILICON EMITTER BIPOLAR-TRANSISTORS

In self-aligned polysilicon emitter transistors a large electric field existing at the periphery of the emitter-base junction under reverse bias can create hot-carrier-induced degradation. The degradation of polysilicon emitter transistor gain under DC stress conditions can be modeled by ΔIB ∝ IRm+ ntn where n 0.5 and m 0.5. The more complex relationships of Δβ(IC, IR, t) and β(IC, I R, t) result naturally from the simple ΔIB model. Using these relationships the device lifetime can be extrapolated over a wide range of reverse stress currents for a given technology.