DEGRADATION DUE TO ELECTRICAL STRESS OF POLY-SI THIN-FILM TRANSISTORS WITH VARIOUS LDD LENGTHS

被引：10

作者：

KIM, YS ^{[1
]}

HAN, MK ^{[1
]}

机构：

[1] SEOUL NATL UNIV,DEPT ELECT ENGN,SEOUL 151742,SOUTH KOREA

来源：

IEEE ELECTRON DEVICE LETTERS | 1995年 / 16卷 / 06期

关键词：

D O I：

10.1109/55.790723

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The degradation phenomena of polycrystalline silicon (poly-Si) thin film transistors (TFT's) with various lightly-doped drain (LDD) length have been investigated, It is observed that the threshold voltage shift due to electrical stress varies with LDD length, The threshold voltage shift after 4 hours electrical stress of V-g = V-d = 30 V in conventional, 0.5 mu m, and 2 mu m LDD poly-Si TFT's are about 2.7 V, 5.2 V, and 0.8 V, respectively,

引用

页码：245 / 247

页数：3

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