HIGH-SPEED AND LARGE NOISE MARGIN TOLERANCE E/D LOGIC GATES WITH LDD STRUCTURE DMTS FABRICATED USING SELECTIVE RIE TECHNOLOGY

被引：12

作者：

HIDA, H

TSUKADA, Y

OGAWA, Y

TOYOSHIMA, H

FUJII, M

SHIBAHARA, K

KOHNO, M

NOZAKI, T

机构：

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 1989年 / 36卷 / 10期

关键词：

D O I：

10.1109/16.40903

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：2223 / 2230

页数：8

共 10 条

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