MINIMUM-SIZE EFFECTS IN ASYMMETRIC TILT-ANGLE-IMPLANTED LDD-WNX-GAAS MESFETS

Asymmetric tilt-angle-implanted LDD-WN(x)-GaAs MESFET's with an optimized transconductance performance are discussed. A tilt-angle implantation is used to reduce the parasitic source resistance below the gate sidewall without increasing short- and narrow-channel effects. This finally leads to a transconductance increase of nearly 25% of submicrometer FET's while the gate source capacitance increase is almost negligible. The influence of the implantation angle on the threshold voltage, transconductance, and Schottky-barrier characteristics are reported. The novel asymmetric tilt-angle-implanted LDD structure is highly suitable for LSI fabrication since the increase of fabrication complexity is insignificant.