A HIGH-SPEED SENSING SCHEME FOR 1T DYNAMIC RAMS UTILIZING THE CLAMPED BIT-LINE SENSE AMPLIFIER

被引：14

作者：

BLALOCK, TN ^{[1
]}

JAEGER, RC ^{[1
]}

机构：

[1] AUBURN UNIV,DEPT ELECT ENGN,ALABAMA MICROELECTR SCI & TECHNOL TR,AUBURN,AL 36849

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1992年 / 27卷 / 04期

关键词：

D O I：

10.1109/4.126552

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A clamped-bit-line sense amplifier (CBLSA) capable of very high-speed operation in one-transistor (1T) DRAM applications has been developed. Results from an experimental test chip demonstrate that the speed of the new circuit is insensitive to bit-line capacitance. Circuit speed is also found to be insensitive to initial bit-line difference voltage. The CBLSA maintains a low-impedance fixed potential on the bit lines during sensing, virtually eliminating sensitivity to inter-bit-line noise coupling and minimizing power supply bounce during sensing. The new sense amplifier operates at higher speeds than conventional circuits and still dissipates less power.

引用

页码：618 / 625

页数：8

共 10 条

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