HOLE TRAPPING PHENOMENA IN THE GATE INSULATOR OF AS-FABRICATED INSULATED GATE FIELD-EFFECT TRANSISTORS

Hole trapping phenomena in SiO2 were examined using an optically assisted hot carrier injection technique on p-channel insulated gate field effect transistors. It was found that only a single, field-dependent, capture-cross-section hole trap is present. The capture cross section of these hole traps at a field of 4 mV/cm across the gate insulator, corresponding to a gate voltage just above the threshold voltage, was found to be 8.5×10 -14 cm2. Injected holes were found to trap with an initial efficiency of approximately 60% at this gate field. Depopulation of trapped holes at room temperature was also examined, and found to be significant. The neutral hole trap density in unirradiated device gate insulators after post-metal annealing was found to be approximately 7.0×1012 cm-2. Based on a study of the threshold voltage shift as a function of gate insulator thickness, coupled with the model recently proposed by Walters and Reisman for determining charge centroid, it appears that for oxides with thicknesses greater than 10 nm, the hole traps lie in a band of finite thickness with a charge centroid 5 nm from the substrate-SiO2 interface. In addition, there exists a layer approximately 3.7 nm thick at each interface that appears void of trapped charge. Therefore, oxides less than 7.4 nm thick should not trap charge, which was found to be the case experimentally. This implies that as devices are scaled down, hole trapping will disappear, which is of particular significance in oxides subjected to ionizing irradiation, either during processing or during use.