DYNAMIC GAAS CAPACITIVELY COUPLED DOMINO LOGIC (CCDL)

Dynamic capacitively coupled domino logic (CCDL) has been proposed as a practical means of implementing low-power and high-speed complex gates. In this paper, the CCDL gate delay characteristics obtained from an analytical model and from test circuits implemented in a 1-mu-m GaAs E/D process are presented. In addition, the feasibility of using CCDL gates to implement practical circuits is demonstrated by the experimental characterization of a 4-b carry-lookahead adder. The adder has a critical delay of 1.1 ns and a power dissipation of 96 mW.