THE ORIGINS OF THE PERFORMANCE DEGRADATION OF IMPLANTED P+ POLYSILICON GATED P-CHANNEL MOSFET WITH WITHOUT RAPID THERMAL ANNEALING

被引:7
作者
HSIEH, JC
FANG, YK
CHEN, CW
TSAI, NS
LIN, MS
TSENG, FC
机构
[1] TAIWAN SEMICOND MFG CO LTD,RES & DEV,HSINCHU,TAIWAN
[2] NATL CHENG KUNG UNIV,DEPT ELECT & COMP ENGN,TAINAN,TAIWAN
关键词
D O I
10.1109/16.285018
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Some anomalous behaviors, such as punchthrough voltage reduction, leakage current increase, and g(m) instability have been found in BF2 implanted p+-polysilicon P-MOSFET's. These effects are supposed due to B-ion penetration. To prevent the B-ion penetration, RTA has been used. Experimental results show that RTA can improve the effect. But, the RTA process can also cause the generation of interface states, gate-induced-drain-leakage increase, and oxide quality degradation. All of the mechanisms of performance degradation are investigated and modeled in detail.
引用
收藏
页码:692 / 697
页数:6
相关论文
共 18 条
  • [1] Chan T. Y., 1987, IEDM TECH DIG, P718
  • [2] INTERFACE-TRAP ENHANCED GATE-INDUCED LEAKAGE CURRENT IN MOSFET
    CHEN, IC
    TENG, CW
    COLEMAN, DJ
    NISHIMURA, A
    [J]. IEEE ELECTRON DEVICE LETTERS, 1989, 10 (05) : 216 - 218
  • [3] CHEN IC, 1985, IEEE J SOLID-ST CIRC, V20, P333
  • [4] SUB-BREAKDOWN DRAIN LEAKAGE CURRENT IN MOSFET
    CHEN, J
    CHAN, TY
    CHEN, IC
    KO, PK
    HU, C
    [J]. IEEE ELECTRON DEVICE LETTERS, 1987, 8 (11) : 515 - 517
  • [5] Chen M., 1988, International Electron Devices Meeting. Technical Digest (IEEE Cat. No.88CH2528-8), P390, DOI 10.1109/IEDM.1988.32838
  • [7] DESIGN TRADEOFFS BETWEEN SURFACE AND BURIED-CHANNEL FETS
    HU, GJ
    BRUCE, RH
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1985, 32 (03) : 584 - 588
  • [8] THE USE OF ULTRATHIN REOXIDIZED NITRIDED GATE OXIDE FOR SUPPRESSION OF BORON PENETRATION IN BF2+-IMPLANTED POLYSILICON GATED P-MOSFETS
    LO, GQ
    KWONG, DL
    [J]. IEEE ELECTRON DEVICE LETTERS, 1991, 12 (04) : 175 - 177
  • [9] ANOMALOUS C-V CHARACTERISTICS OF IMPLANTED POLY MOS STRUCTURE IN N+/P+ DUAL-GATE CMOS TECHNOLOGY
    LU, CY
    SUNG, JM
    KIRSCH, HC
    HILLENIUS, SJ
    SMITH, TE
    MANCHANDA, L
    [J]. IEEE ELECTRON DEVICE LETTERS, 1989, 10 (05) : 192 - 194
  • [10] POLYSILICON CAPACITOR FAILURE DURING RAPID THERMAL-PROCESSING
    MCGRUER, NE
    OIKARI, RA
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1986, 33 (07) : 929 - 933