DESIGN AND PERFORMANCE OF 0.1-MU-M CMOS DEVICES USING LOW-IMPURITY-CHANNEL TRANSISTORS (LICTS)

0.1-mu-m CMOS devices using low-impurity-channel transistors (LICT's) with dual-polysilicon gates have been fabricated by nondoped epitaxial growth technology, high-pressure oxidation of field oxide, and electron-beam lithography. These devices, with gate lengths of 0.135-mu-m, achieved normal transistor operation at both 300 and 77 K using 1.5-V supply voltage. Maximum transconductances are 203 mS/mm for nMOS transistors and 124 mS/mm for pMOS transistors at 300 K. Low-impurity channels grown on highly doped wells provide low threshold voltages of about 0.35 V for nMOS transistors and about -0.15 V for pMOS transistors at 77 K, and preserve good turn-offs with subthreshold swings of 25 mV/decade at 77 K. LICT's suppress short-channel effects more effectively, compared with conventional devices with nearly uniform dopings.