IMPLEMENTING QML FOR RADIATION HARDNESS ASSURANCE

Statistical process control (SPC) of technology parameters relevant to radiation hardness, test structure to IC correlation, and extrapolation from laboratory to threat scenarios are keys to implementing QML for radiation hardness assurance in a cost-effective manner. Data from approximately 300 wafer lots fabricated in Sandia's 4/3-µm and CMOS IIIA (2-µm) technologies are used to demonstrate approaches to, and highlight issues associated with, implementing QML for radiation-hardened CMOS in space applications. An approach is demonstrated to implement QML for single-event upset (SEU) immunity on 16k SRAMs that involves relating values of feedback resistance to system error rates. It is seen that the process capability indices, Cp and Cpk, for the manufacture of 400 kΩ feedback resistors required to provide SEU tolerance do not conform to “6σ” quality standards. For total-dose, ΔVit shifts measured on transistors are correlated with circuit response in the space environment. SPC is illustrated for ΔVit, and violations of SPC rules are interpreted in terms of continuous improvement. Finally, design validation for SEU, and quality conformance inspections for total-dose, are identified as major obstacles to cost-effective QML implementation. Techniques and tools that will help QML provide real cost savings are identified as physical models, 3D device-plus-circuit codes, and improved design simulators. © 1990 IEEE