CIRCUIT TECHNIQUES FOR 1.5-3.6-V BATTERY-OPERATED 64-MB DRAM

Circuit techniques for battery-operated DRAM's which cover supply voltages from 1.5 to 3.6 V (universal V(CC)), as well as their applications to an experimental 64-Mb DRAM, are presented. The proposed universal-V(CC) DRAM concept features a low-voltage (1.5 V) DRAM core and an on-chip power supply unit optiized for the operation of the DRAM. A circuit technique for oxide-stress relaxation is proposed to improve high-voltage sustaining characteristics while only scaled MOSFET's are used in the entire chip. This technique increases sustaining voltage by about 1.5 V when compared with conventional circuits and allows scaled MOSFET's to be used for the circuits, which can be operated from an external V(CC) of up to 4 V. A two-way power supply scheme is also proposed to suppress the internal voltage fluctuation within 10% when the DRAM is operated from external power supply voltages ranging from 1.5 to 3.6 V. An experimental 1.5-3.6-V 64-Mb DRAM is designed based on these techniques and fabricated by using 0.3-mu-m electron-beam lithography. An almost constant access time of 70 ns is obtained over a supply voltage range from 1.5 to 3.6 V. This indicates that battery operation is a promising target for future DRAM's.