A MARKOV CHAIN-BASED YIELD FORMULA FOR VLSI FAULT-TOLERANT CHIPS

A new yield calculation method for the yield formula of fault-tolerant VLSI chips is introduced, which improves existing methods and puts together generalities, ease of computation, and predictability in approximation levels. The innovative part of the method is concerned with the evaluation of the probability that the chip is acceptable given n defects. This is done by introduction of a Markov chain model, in which each state represents an operating chip configuration and the state transitions take place by the presence of manufacturing defects. Comparisons are made with three existing yield calculation methods to prove the "ease of use," the "accuracy," and the "representativeness" characteristics of the new proposed one.