SCALING OF MOS TECHNOLOGY TO SUBMICROMETER FEATURE SIZES

被引:30
作者
MEAD, CA
机构
[1] California Institute of Technology, Pasadena, 91125, CA
关键词
D O I
10.1007/BF01250732
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Industries based on MOS technology now play a prominent role in the developed and the developing world. More importantly, MOS technology drives a large proportion of innovation in many technologies. It is likely that the course of technological development depends more on the capability of MOS technology than on any other technical factor. Therefore, it is worthwhile investigating the nature and limits of future improvements to MOS fabrication. The key to improved MOS technology is reduction in feature size. Reduction in feature size, and the attendant changes in device behavior, will shape the nature of effective uses of the technology at the system level. This paper reviews recent, and historical, data on feature scaling and device behavior, and attempts to predict the limits to this scaling. We conclude with some remarks on the system-level implications of feature size as the minimum size approaches physical limits.
引用
收藏
页码:9 / 25
页数:17
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