DEEP-LEVEL TRAPPING IN ION-IMPLANTED INP JFETS

The trapping mechanisms which cause low-frequency transconductance and output resistance dispersion in ion-implanted InP JFETs are examined. The trapping activity at room temperature occurs primarily between 100 Hi and 1 MHz and is caused by electron traps located at the access region surface and in the substrate below the channel. By monitoring the characteristic frequencies of the dispersion as a function of temperature, the activation energies of the traps were determined. The trapping mechanism responsible for the low-field transconductance dispersion appears to be a surface state with an activation energy of 0.28 eV. The output resistance dispersion indicates several traps with major ones at 0.44 and 0.55 eV at operating bias. Low-frequency noise peaks caused by the traps were found to be consistent with the dispersion measurements. After subtracting the trap Lorentzian contributions, the Hooge parameter was found to be 4 x 10(-4).