BLOCK ORGANIZED 64-KBIT CCD MEMORY

被引：12

作者：

VARSHNEY, RC ^{[1
]}

VENKATASWARAN, K ^{[1
]}

机构：

[1] FAIRCHILD SEMICONDUCTOR,DIV RES & DEV,PALO ALTO,CA 94304

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1978年 / 13卷 / 05期

关键词：

D O I：

10.1109/JSSC.1978.1051119

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：681 / 687

页数：7

共 11 条

[1] EXPERIMENTAL VERIFICATION OF CHARGE COUPLED DEVICE CONCEPT [J].

AMELIO, GF ;

TOMPSETT, MF ;

SMITH, GE .

BELL SYSTEM TECHNICAL JOURNAL, 1970, 49 (04) :593-+

[2]

AMELIO GF, 1976, 3RD P INT C TECHN AP, P159

[3] CHARGE COUPLED SEMICONDUCTOR DEVICES [J].

BOYLE, WS ;

SMITH, GE .

BELL SYSTEM TECHNICAL JOURNAL, 1970, 49 (04) :587-+

[4] DESIGN OF A 16-384-BIT SERIAL CHARGE-COUPLED MEMORY DEVICE [J].

CHOU, S .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1976, 11 (01) :10-18

[5]

COLLINS DR, 1973, ISSCC DIG TECH PAPER, P136

[6] CCD LINE ADDRESSABLE RANDOM-ACCESS MEMORY (LARAM) [J].

GUNSAGAR, KC ;

GUIDRY, MR ;

AMELIO, GF .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1975, 10 (05) :268-273

[7] CHARGE-COUPLES DIGITAL CIRCUITS [J].

KOSONOCKY, WF ;

CARNES, JE .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1971, SC 6 (05) :314-+

[8] 64-KBIT BLOCK ADDRESSED CHARGE-COUPLED MEMORY [J].

MOHSEN, AM ;

BOWER, RW ;

WILDER, EM ;

ERB, DM .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1976, 11 (01) :49-58

[9]

ROSENBAUM SD, 1976, IEEE J SOLID STATE C, V11, P40

[10] BYTE ORGANIZED NMOS-CCD MEMORY WITH DYNAMIC REFRESH LOGIC [J].

VARSHNEY, RC ;

GUIDRY, MR ;

AMELIO, GF ;

EARLY, JM .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1976, 11 (01) :18-24

← 1 2 →