PROCESS MODELING OF INTEGRATED-CIRCUIT DEVICE TECHNOLOGY

[1] BORON IN NEAR-INTRINSIC (100) AND (111) SILICON UNDER INERT AND OXIDIZING AMBIENTS-DIFFUSION AND SEGREGATION [J]. JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1978, 125 (05) : 813 - 819

[2] IMPURITY REDISTRIBUTION IN SIO2-SI DURING OXIDATION - NUMERICAL-SOLUTION INCLUDING INTERFACIAL FLUXES [J]. JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1979, 126 (11) : 1939 - 1945

[3] MODELS FOR COMPUTER-SIMULATION OF COMPLETE IC FABRICATION PROCESS [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1979, 14 (02) : 412 - 422

[4] IMPURITY REDISTRIBUTION AND JUNCTION FORMATION IN SILICON BY THERMAL OXIDATION [J]. BELL SYSTEM TECHNICAL JOURNAL, 1960, 39 (04): : 933 - 946

[5] BARTON RW, 1980, THIN FILM INTERFACES

[6] INJECTION MODEL - STRUCTURE-ORIENTED MODEL FOR MERGED TRANSISTOR LOGIC (MTL) [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1974, SC 9 (05) : 218 - 227

[7] BOREL J, 1973, ISSCC TECH DIG 0214, P102

[8] EFFECT OF THE DRAIN-SOURCE VOLTAGE ON DOPANT PROFILES OBTAINED FROM THE DC MOSFET PROFILE METHOD [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1980, 27 (12) : 2273 - 2277

[9] CHIN DJ, 1980, DEC IEDM, P223

[10] HIGH-SPEED IMPLEMENTATION AND EXPERIMENTAL EVALUATION OF MULTILAYER SPREADING RESISTANCE ANALYSIS [J]. JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1978, 125 (07) : 1170 - 1176

[1] BORON IN NEAR-INTRINSIC (100) AND (111) SILICON UNDER INERT AND OXIDIZING AMBIENTS-DIFFUSION AND SEGREGATION [J]. JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1978, 125 (05) : 813 - 819

[2] IMPURITY REDISTRIBUTION IN SIO2-SI DURING OXIDATION - NUMERICAL-SOLUTION INCLUDING INTERFACIAL FLUXES [J]. JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1979, 126 (11) : 1939 - 1945

[3] MODELS FOR COMPUTER-SIMULATION OF COMPLETE IC FABRICATION PROCESS [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1979, 14 (02) : 412 - 422

[4] IMPURITY REDISTRIBUTION AND JUNCTION FORMATION IN SILICON BY THERMAL OXIDATION [J]. BELL SYSTEM TECHNICAL JOURNAL, 1960, 39 (04): : 933 - 946

[5] BARTON RW, 1980, THIN FILM INTERFACES

[6] INJECTION MODEL - STRUCTURE-ORIENTED MODEL FOR MERGED TRANSISTOR LOGIC (MTL) [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1974, SC 9 (05) : 218 - 227

[7] BOREL J, 1973, ISSCC TECH DIG 0214, P102

[8] EFFECT OF THE DRAIN-SOURCE VOLTAGE ON DOPANT PROFILES OBTAINED FROM THE DC MOSFET PROFILE METHOD [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1980, 27 (12) : 2273 - 2277

[9] CHIN DJ, 1980, DEC IEDM, P223

[10] HIGH-SPEED IMPLEMENTATION AND EXPERIMENTAL EVALUATION OF MULTILAYER SPREADING RESISTANCE ANALYSIS [J]. JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1978, 125 (07) : 1170 - 1176