Challenges of back end of the line for sub 65 nm generation

被引：55

作者：

Fayolle, M

Passemard, G

Louveau, O

Fusalba, F

Cluzel, J

机构：

[1] CEA Grenoble, LETI, F-38054 Grenoble 9, France

[2] STMicroelect, F-38926 Crolles, France

来源：

MICROELECTRONIC ENGINEERING | 2003年 / 70卷 / 2-4期

关键词：

interconnect; ultra-low-K dielectric; porous dielectric; integration; reliability; size effect; 65 nm node; 45 nm node;

D O I：

10.1016/S0167-9317(03)00467-2

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a review of interconnect challenges for sub 65 nm node. From this generation, porous ultra low K (ULK) dielectric materials (dielectric constant k<2.1) are required. Their porosity makes integration very difficult, due to the mechanical weakness and process interaction issues (especially during stripping, CVD metal barrier deposition...). To overcome these process incompatibilities and keep the 'effective dielectric constant' low, dual damascene architecture becomes more and more complex and requires additional steps (porosity sealing treatment, degas steps, supercritical CO2 clean, low k dielectric barrier, self aligned barrier...). Possible contamination trapped in the porosity (moisture, metallic residues...), and lower thermo-mechanical properties of ULK will probably impede reliability. Copper resistivity increase with dimension shrinkage will also be an extra issue. (C) 2003 Elsevier B.V. All rights reserved.

引用

页码：255 / 266

页数：12

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