The effects of plasma-induced damage on transistor degradation and the relationship to Field Programmable Gate Array performance

被引：11

作者：

Pagaduan, FE ^{[1
]}

Lee, JKJ ^{[1
]}

Vedagarbha, V ^{[1
]}

Lui, K ^{[1
]}

Hart, MJ ^{[1
]}

Gitlin, D ^{[1
]}

Takaso, T ^{[1
]}

Kamiyama, S ^{[1
]}

Nakayama, K ^{[1
]}

机构：

[1] Xilinx Inc, San Jose, CA 95124 USA

来源：

39TH ANNUAL PROCEEDINGS: INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM 2001 | 2001年

关键词：

D O I：

10.1109/RELPHY.2001.922921

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The impact of plasma-induced damage on the speed performance of a Field Programmable Gate Array (FPGA) is presented. It was found that FPGA speed degradation induced by product reliability burn-in was directly related to a large negative threshold voltage, Vt, shift of the surface channel PMOS induced by (-) bias temperature (BT) stress. Such Negative Bias Temperature Instability (NBTI) in the PMOS was shown to be related to specific back-end plasma processing steps. An overall reduction in NBTI of the PMOSFET was observed when certain plasma processing steps were eliminated which in turn resulted in the reduction of FPGA performance degradation.

引用

页码：315 / 318

页数：4

共 10 条

[1] Controlling plasma charge damage in advanced semiconductor manufacturing-challenge of small feature size device, large chip size, and large wafer size [J].