Ultralow-power SRAM technology

An ultralow-standby-power technology has been developed in both 0.18-mum and 0.13-mum lithography nodes for embedded and standalone SRAM applications. The ultralow-leakage six-transistor (6T) SRAM cell sizes are 4.81 mum(2) and 2.34 mum(2) corresponding respectively to the 0.18-mum and 0.13-mum design dimensions. The measured array standby leakage is equal to an average cell leakage current of less than 50 fA per cell at 1.5 V, 25degreesC and is less than 400 fA per cell at 1.5 V, 85degreesC. Dual gate oxides of 2.9 nm and 5.2 nm provide optimized cell leakage, I/O compatibility, and performance. Analyses of the critical parasitic leakage components and paths within the 6T SRAM cell are reviewed in this paper. In addition to the well-known gate-oxide leakage limitation for ULP technologies, three additional limits facing future scaled ULP technologies are discussed.