VTCMOS characteristics and its optimum conditions predicted by a compact analytical model

被引：11

作者：

Im, H ^{[1
]}

Inukai, T ^{[1
]}

Gomyo, H ^{[1
]}

Hiramoto, T ^{[1
]}

Sakurai, T ^{[1
]}

机构：

[1] Univ Tokyo, Inst Ind Sci, Minato Ku, Tokyo 106, Japan

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2003年 / 11卷 / 05期

基金：

日本学术振兴会;

关键词：

analytical model; body effect; low power; substrate bias; variable-threshold-voltage CMOS (VTCMOS);

D O I：

10.1109/TVLSI.2003.814320

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A compact analytical model of variable-threshold-voltage CMOS (VTCMOS) is proposed to study the active on current, linking it with the standby off-current characteristics. Comparisons of modeled results to both numerical simulations and experimental data are made with an excellent agreement. It is clearly demonstrated using the model that speed degradation due to low supply voltage can be compensated by the VTCMOS scheme, even with smaller power. Influence of the short channel effect (SCE) on the performance of VTCMOS is investigated in terms of a new parameter, dS/dgamma, both qualitatively and quantitatively. It is found that the SCE degrades the VTCMOS performance. Issues on the optimum conditions of VTCMOS and the performance of series-connected VTCMOS circuits are also discussed.

引用

页码：755 / 761

页数：7

共 10 条

[1]

Hiramoto T, 2000, IEICE T ELECTRON, VE83C, P161

[2] Optimum device parameters and scalability of variable threshold voltage complementary MOS (VTCMOS) [J].

Hiramoto, T ;

Takamiya, M ;

Koura, H ;

Inukai, T ;

Gomyo, H ;

Kawaguchi, H ;

Sakurai, T .

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2001, 40 (4B) :2854-2858

[3]

Im H, 2002, ISLPED'02: PROCEEDINGS OF THE 2002 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, P13, DOI 10.1109/LPE.2002.1029504

[4] Variable threshold voltage CMOS (VTCMOS) in series connected circuits [J].

Inukai, T ;

Hiramoto, T ;

Sakurai, T .

ISLPED'01: PROCEEDINGS OF THE 2001 INTERNATIONAL SYMPOSIUM ON LOWPOWER ELECTRONICS AND DESIGN, 2001, :201-206

[5]

INUKAI T, 1998, FUNDAMENTALS MODERN

[6] Optimum conditions of body effect factor and substrate bias in variable threshold voltage MOSFETs [J].

Koura, H ;

Takamiya, M ;

Hiramoto, T .

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2000, 39 (4B) :2312-2317

[7] A 0.9-V, 150-MHz, 10-mW, 4 mm(2), 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme [J].

Kuroda, T ;

Fujita, T ;

Mita, S ;

Nagamatsu, T ;

Yoshioka, S ;

Suzuki, K ;

Sano, F ;

Norishima, M ;

Murota, M ;

Kako, M ;

Kinugawa, M ;

Kakumu, M ;

Sakurai, T .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996, 31 (11) :1770-1779

[8]

MIZUNO H, 1999, P IEEE INT SOL STAT, P280

[9] A SIMPLE MOSFET MODEL FOR CIRCUIT ANALYSIS [J].

SAKURAI, T ;

NEWTON, AR .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1991, 38 (04) :887-894

[10] DELAY ANALYSIS OF SERIES-CONNECTED MOSFET CIRCUITS [J].

SAKURAI, T ;

NEWTON, AR .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1991, 26 (02) :122-131

← 1 →