Effects of base layer thickness on reliability of CVD Si3N4 stack gate dielectrics

被引：15

作者：

Eriguchi, K ^{[1
]}

Harada, Y ^{[1
]}

Niwa, M ^{[1
]}

机构：

[1] Matsushita Elect Ind Co Ltd, ULSI Proc Technol Dev Ctr, Semicond Co, Minami Ku, Kyoto 6018413, Japan

来源：

MICROELECTRONICS RELIABILITY | 2001年 / 41卷 / 04期

关键词：

D O I：

10.1016/S0026-2714(00)00247-X

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Effects of the base layer in Si3N4/SiON stack gate dielectrics, in particular, the physical thickness of the base layer, on the dielectric reliability, MOSFET performance and process controllability are investigated. It is found that the electrical characteristics such as TDDB lifetime as well as the Si3N4 film property in Si3N4/SiON stack dielectrics with the same capacitance oxide equivalent thickness strongly depend on the SiON-base layer thickness. From the TDDB measurements for both stress polarities and from the Si3N4 stoichiometry by the X-ray photoelectron spectroscopy analysis, the optimum SiON-base layer thickness is determined to be approximately 1 nm, in order to obtain longer TDDB lifetime and surperior n-ch MOSFET performance. The obtained results are considered to attribute to the nitrogen profile in the Si3N4/SiON stack dielectrics and the strained layer thickness near SiON/Si interface. (C) 2001 Elsevier Science Ltd. All rights reserved.

引用

页码：587 / 595

页数：9

共 16 条

[1]

Byoung Hun Lee, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), P133, DOI 10.1109/IEDM.1999.823863

[2] CMOS Metal Replacement Gate Transistors using tantalum pentoxide gate insulator [J].

Chatterjee, A ;

Chapman, RA ;

Joyner, K ;

Otobe, M ;

Hattangady, S ;

Bevan, M ;

Brown, GA ;

Yang, H ;

He, Q ;

Rogers, D ;

Fang, SJ ;

Kraft, R ;

Rotondaro, ALP ;

Terry, M ;

Brennan, K ;

Aur, SW ;

Hu, JC ;

Tsai, HL ;

Jones, P ;

Wilk, G ;

Aoki, M ;

Rodder, M ;

Chen, IC .

INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST, 1998, :777-780

[3] STUDY OF THE COMPOSITION OF THIN DIELECTRICS GROWN ON SI IN A PURE N2O AMBIENT [J].

CHU, TY ;

TING, W ;

AHN, JH ;

LIN, S ;

KWONG, DL .

APPLIED PHYSICS LETTERS, 1991, 59 (12) :1412-1414

[4] Influence of 1nm-thick structural "strained-layer" near SiO2/Si interface on sub-4nm-thick gate oxide reliability [J].

Eriguchi, K ;

Harada, Y ;

Niwa, M .

INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST, 1998, :175-178

[5] Effects of strained layer near SiO2-Si interface on electrical characteristics of ultrathin gate oxides [J].

Eriguchi, K ;

Harada, Y ;

Niwa, M .

JOURNAL OF APPLIED PHYSICS, 2000, 87 (04) :1990-1995

[6] Tunneling leakage current in oxynitride: Dependence on oxygen/nitrogen content [J].

Guo, X ;

Ma, TP .

IEEE ELECTRON DEVICE LETTERS, 1998, 19 (06) :207-209

[7] RELATIONSHIP BETWEEN MOSFET DEGRADATION AND HOT-ELECTRON-INDUCED INTERFACE-STATE GENERATION [J].

HSU, FC ;

TAM, S .

IEEE ELECTRON DEVICE LETTERS, 1984, 5 (02) :50-52

[8] Ultra thin (<3nm) high quality nitride/oxide stack gate dielectrics fabricated by in-situ rapid thermal processing [J].

Kim, BY ;

Luan, HF ;

Kwong, DL .

INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST, 1997, :463-466

[9] Circuit requirement and integration challenges of thin gate dielectrics for ultra small MOSFETs [J].

Liu, CT .

INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST, 1998, :747-750

[10]

Luan H. F., 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), P141, DOI 10.1109/IEDM.1999.823865

← 1 2 →