An analytical grain-barrier height model and its characterization for intrinsic poly-Si thin-film transistor

被引：45

作者：

Chen, HL ^{[1
]}

Wu, CY

机构：

[1] Natl Chiao Tung Univ, Adv Semicond Device Res Lab, Hsinchu, Taiwan

[2] Natl Chiao Tung Univ, Inst Elect, Hsinchu, Taiwan

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 1998年 / 45卷 / 10期

关键词：

GB states; grain-barrier height; grain size; intrinsic poly-Si TFT;

D O I：

10.1109/16.725260

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An analytical model for the grain-barrier height of the intrinsic poly-Si thin-film transistors (TFT's) is developed, in which the grain-barrier height for the applied gate voltage smaller than the threshold voltage is obtained by solving the charge neutrality equation and the grain-barrier height for the applied gate voltage larger than the threshold voltage is obtained by using the quasi-two-dimensional (2-D) method. Good agreements between experimental and simulation results are obtained for wide gate voltage range.

引用

页码：2245 / 2247

页数：3

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