Opportunities and Challenges for Germanium and Silicon-Germanium Channel p-FETs

被引：6

作者：

Bedell, S. W. ^{[1
]}

Daval, N. ^{[2
]}

Fogel, K. ^{[1
]}

Shimizu, K. ^{[3
]}

Ott, J. ^{[1
]}

Newbury, J. ^{[1
]}

Sadana, D. K. ^{[1
]}

机构：

[1] IBM Res, Yorktown Hts, NY 10598 USA

[2] SOITEC Assignee IBM Res, Yorktown Hts, NY 10598 USA

[3] Univ Tokyo, IIS, Tokyo, Japan

来源：

ADVANCED GATE STACK, SOURCE/DRAIN, AND CHANNEL ENGINEERING FOR SI-BASED CMOS 5: NEW MATERIALS, PROCESSES, AND EQUIPMENT | 2009年 / 19卷 / 01期

关键词：

HIGH-KAPPA GATE; GE PMOSFETS; METAL GATE; SUBSTRATE;

D O I：

10.1149/1.3118941

中图分类号：

O646 [电化学、电解、磁化学];

学科分类号：

081704 ;

摘要：

The electrical behavior of SiGe and pure Ge channel p-FET devices will be presented and discussed in this paper. By fabricating short channel SiGe, relaxed Ge and strained Ge channel devices with scaled high-kappa/metal gate stacks, we demonstrate three main advantages of using these types of devices: i) more aggressive T-INV scaling of the gate dielectric due to lower temperature processing, ii) band gap engineering to allow better control of threshold voltage and possibly iii) lower external resistance due to the higher B activation in these materials. The main drawback inherent to relaxed Ge and biaxially strained Ge and SiGe channels is that the ability to have improved transport properties without the need for external stressors always seems to come with a large penalty in off state leakage. The I-ON and I-OFF in these devices are compared to recent work by others and a general trend is observed.

引用

页码：155 / +

页数：2

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