Recovery of the NBTI-stressed ultrathin gate p-MOSFET: The role of deep-level hole traps

Under a static negative-bias temperature stress, the negative threshold-voltage V-t shift (extracted from the de current-voltage characteristic) of the direct-tunneling gate p-MOSFET is found to be substantially larger than that calculated based on the interface-state density measured using the charge-pumping method. Device-recovery characteristics from bipolar gate stress show that interface states alone cannot entirely account for the V-t shift, and indicate that a substantial number of positive oxide charges are also generated during stress. Stability of the increased V-t shift under a negative dc gate biasing and unipolar ac gate pulsing implies that these positive charges are deep-level hole traps with energy states above the Si conduction-band edge. Because the defect states are outside the energy window of direct electron tunneling, their long relaxation time plays an important role in the slow recovery transient of the p-MOSFET.