Impact of tunnel-oxide nitridation on endurance and read-disturb characteristics of Flash E(2)PROM devices

Threshold-voltage window closure in non-volatile memory (NVM) devices is known to originate from charge trapping in the dielectric underneath the floating gate (FG dielectric). In this paper, it is shown that oxide nitridation lowers the generation rate of neutral electron traps and, consequently, reduces the amount of trapped charge. Therefore, FG dielectric nitridation improves the endurance characteristics of NVM devices. Also, write/erase (W/E) degradation of NVM devices results in a Stress Induced Leakage Current (SILC) through the FG dielectric, enhancing read-disturb. The conduction mechanism of the SILC being trap-assisted tunnelling, FG dielectric nitridation is expected to reduce the SILC. However, the lower trap generation rate in the nitrided oxides is compensated by an enhanced trap-assisted conduction efficiency, resulting in nearly the same SILC as compared to conventional oxides. Therefore, read-disturb is barely affected by nitridation of the FG dielectric.