Statistical profiling of SILC spot in flash memories

被引：10

作者：

Ielmini, D ^{[1
]}

Spinelli, AS

Lacaita, AL

Visconti, A

机构：

[1] Politecn Milan, Dipartimento Elettr & Informat, I-20133 Milan, Italy

[2] Univ Studi Insubria, Dipartimento Sci Chim Fis & Matemat, I-22100 Como, Italy

[3] Inst Nazl Fis Mat, Unita Como, I-22100 Como, Italy

[4] STMicroelect, Cent Res & Dev, I-20041 Agrate Brianza, Italy

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2002年 / 49卷 / 10期

关键词：

EPROM; failure analysis; leakage currents; reliability testing;

D O I：

10.1109/TED.2002.803636

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new experimental technique for evaluating the position of the oxide weak spot responsible for the stress-induced leakage current (SILC) in Flash memories is presented. The oxide field along the channel is modified by drain biasing, and the gate current is then monitored. The position of the leakage spot can be determined by the shift in the gate current-voltage (I-V) characteristics. Experimental results on Flash memory arrays reveal a strong localization of SILC in correspondence of the drain Junction, due to the cooperation effects of program/erase (P/E) operations. The technique can be used to optimize the P/E conditions for maximum device reliability.

引用

页码：1723 / 1728

页数：6

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