Electrical features of the metal-thin porous silicon-silicon structure

This paper considers a theoretical model of the metal-tunnel interface layer-thin porous silicon-p-Si structure. A diffusion-drift equation at the appropriate boundary conditions is solved to clarify a mechanism of the carriers' transport. The voltage drop distribution along the structure is calculated by solving the equations under the condition of continuity of the vector of the electrostatic induction. The obtained analytical expressions allow one to analyse the contribution of the interface layer, porous silicon and surface electron states to the electrical behaviour of the structure. Some parameters of the model are defined from the comparison of experimental I-lr and C-V characteristics with theoretical values for the Pd-porous silicon (60% of porosity)-p-Si structures having different thicknesses of porous silicon layers. The defined barrier height e(phi 0) ranged from 0.45 to 0.47 eV, the interface layer consisted of mainly the native oxide achieved up to 3.0 nm and did not depend on the time of Si electrochemical etching. The evidence that part of the voltage drops on the surface electron states is ensued by comparing the experimental high frequency C-V curves with steady-state I-V curves. Thickening of the porous silicon layer results in a shift in the energetic band of the surface electronic states.