A 14-NS 4-MB CMOS DRAM WITH 300-MW ACTIVE POWER

被引:11
作者
KIRIHATA, T
DHONG, SH
KITAMURA, K
SUNAGA, T
KATAYAMA, Y
SCHEUERLEIN, RE
SATOH, A
SAKAUE, Y
TOBIMATSU, K
HOSOKAWA, K
SAITOH, T
YOSHIKAWA, T
HASHIMOTO, H
KAZUSAWA, M
机构
[1] IBM JAPAN LTD,YASU TECHNOL APPL LAB,YASU,JAPAN
[2] IBM RES,TOKYO RES LAB,CHIYODA KU,TOKYO 102,JAPAN
[3] IBM CORP,LOS GATOS LAB,LOS GATOS,CA 95134
[4] IBM CORP,THOMAS J WATSON RES CTR,YORKTOWN HTS,NY 10598
关键词
D O I
10.1109/4.149425
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A 4-Mb high-speed DRAM (HSDRAM) has been developed and fabricated by using 0.7-mu-m L(eff) CMOS technology with PMOS arrays inside n-type wells and p-type substrate plate trench cells. The 13.18 x 6.38-mm2 chip, organized as either 512K word x 8 b or 1M word x 4 b, achieves a nominal random-access time of 14 ns and a nominal column-access time of 7 ns, with a 3.6-V V(cc) and provision of address multiplexing. The high level of performance is achieved by using a short-signal-path architecture with center bonding pads and a pulsed sensing scheme with a limited bit-line swing. A fast word-line boosting scheme and a two-stage word-line delay monitor provide fast word-line transition and detection. A new data output circuit, which interfaces a 3.6-V V(cc) to a 5-V bus with an NMOS-only driver, also contributes to the fast access speed by means of a preconditioning scheme and a boosting scheme. Limiting the bit-line voltage swing for bit-line sensing results in a low power dissipation of 300 mW for a 60-ns cycle time.
引用
收藏
页码:1222 / 1228
页数:7
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